Abstract
Present-day computationally intensive on-chip applications consume much area and energy. Multi-level cells (MLCs) capable of storing two-bit information can reduce this area and energy consumption. Spintronics-based MLCs are suitable for on-chip memory with salient features like nonvolatility, high endurance, density, zero leakage, etc. Even though spintronic-based MLCs perform well regarding leakage power, speed, and thickness, they require a large switching current that increases energy dissipation during the write operation. Also, external sensing and feedback circuits lead to power and area overheads. This paper proposes a new highperformance Voltage Controlled Spin-Orbit Torque (VGSOT) based parallel MLC that uses Magnetic Tunnel Junctions (MTJs) with peculiar characteristics. The novel approach is to configure the MTJs with different retention times. The proposed model has reduced critical current for switching and write energy compared to conventional MLC due to the decreased energy barrier for switching in the MTJ. The energy barrier is reduced by tuning the retention time of the MTJ, which can be done by modulating the geometrical and physical parameters. Further, the flaws like leakage power, scaling, and the threshold voltage of conventional CMOS transistors in the read and write channel of the presented MLC are compensated by a Carbon nanotube Field Effect Transistor (CNFET). The comprehensive simulations are used to confirm the functionality of the proposed design using a 45 nm Cadence virtuoso. The VGSOT-based MLC’s read-and-write circuit eliminates a sense amplifier and bistable feedback, making it radiation resistant. Compared to pioneering MLC architectures, the design reduces critical switching current by 50% and write energy by 42% for a 2-bit memory cell.
Cite this article as: A. P. B. and T. S. Warrier, “High-performance multi-level cell design using reduced retention time spintronics device,” Electrica, Published online September 9, 2024. doi: 10.5152/electrica.2024.23037.