Speed, power, and area are the parameters to be considered while designing any integrated circuits including adder circuits. Low-power computation circuits play an important role in the very large-scale integration (VLSI) industry. Carry select adder (CSLA) is one of the fastest adders available and used to combat carry rippling. The square root of carry select adder (SCSLA) is a special case of CSLA. Since the SCSLA functions at high speed, it becomes vital to minimize the power dissipation and optimize the entire adder circuit. Adaptive voltage level at source (AVLS) is a technique used to minimize the power utilization of the circuit by decreasing the supply voltage. True-single phase clocking (TSPC) is used to design D flip-flop which reduces both the area and power. The proposed 16-bit adder architectures, one with AVLS normal TSPC-based D flip-flop and the other with AVLS modified TSPC D flip-flop has power reduction of 53.91% and 58.12% respectively, when compared with existing architectures in complementary metal-oxide-semiconductor (CMOS) 180 nm technology. Also, the proposed architectures, when implemented in CMOS 45 nm technology showed a power reduction of 82.75% and 82.93% respectively. The circuits are realized using Cadence Virtuoso and simulated using Cadence Spectre. Both the adders are power-efficient and operate at high speed.
Cite this article as: B. S. Premananda, K. J. Nikhil and S. H. Managoli. “Low Power Square Root Carry Select Adder using AVLS-TSPC-based D Flip-flop,” Electrica, 22(1), 109-118, Jan. 2022.