Power-Efficient Viterbi Decoder Architecture and Field Programmeble Gate Arrays Fpga Implementation

A Viterbi decoder systemcomprises a convolutional encoder and Viterbi decoder. In general, the codewords generated from the input series of convolutional encoder arrive at thedecoder through a noisy channel; however, the channel noise can causecorruption of code words. The Viterbi decoder extracts the original inputmessage from the corrupted data using the Viterbi algorithm based on themaximum likelihood principle. A Viterbi decoder mainly comprises four essentialunits: a branch metrics unit, add-compare-select unit, path metrics unit, andsurvivor-path memory unit. Related complex calculations are repeated in theseunits at each clock cycle. In this study, a power- and area-efficient Viterbidecoder architecture that also reduces the computational complexity isproposed. Initially, a hard-decision Viterbi decoder system architecture designfor Very Large Scale Integration (VLSI) realization was fulfilled without anyfurther improvement to compare the performance of fundamental and improveddesigns with respect to power consumption. The initial design constitutes anessential base for the improved power- and area-efficient Viterbi decoderarchitecture. The improvements were made to achieve the less complex andpower-efficient architectural system design. The performance of the proposedarchitecture was tested by a fieldprogrammable gate array (FPGA) platform, andthe results have been reported. The architectural design is described using theVerilog hardware description language for comparing the related tests andperformance of FPGA platform.