Warpage Reduction for Power MOSFET Wafers


Faculty of Engineering and Green Technology, Universiti Tunku Abdul Rahman, Kampar, Malaysia


Department of Electronics and Communication Engineering, Guru Nanak Dev Engineering College, Karnataka, India

ELECTRICA 2021; 21: 173-179
DOI: 10.5152/electrica.2021.21019
Read: 186 Downloads: 60 Published: 27 May 2021

Wafer warpage is a baseline issue faced by semiconductor manufacturers and is, in fact, particularly conspicuous among those which are involved in the fabrication of power metal oxide semiconductor field effect transistors (MOSFETs). This is because vertical MOSFETs experience larger warpage effects compared with their conventional lateral counterparts. Wafers with warpage exceeding its critical value fail to be chucked by vacuum adsorption during the automatic handling process; the devices fabricated in the wafer face reliability issues as well. This paper presents an analysis on various mechanisms employed to reduce warpage in power MOSFET wafers. The warpage behavior was examined by varying the backside metallization (BSM) thickness, the sputtering power for film deposition and the wafer’s temperature (i.e., a cryogenic condition was introduced into the process). The results suggest that both the BSM thickness and wafer’s temperature do not manifest a clear correlation with the wafer warpage when the front-end fabrication process is completed. The wafer bow level was, however, found to be in direct proportion with the magnitude of the sputtering power. When the sputtering power is reduced, less residual stress is induced to deform the wafer structure. Hence, the sputtering power could be adjusted to ensure that the warpage effect stays below its critical value. 

Cite this article as: K. K. Yeap, H. Nisar, V. Dakulagi, “Warpage Reduction for Power MOSFET Wafers”, Electrica, vol. 21, no. 2, pp. 173-179, May, 2021.

EISSN 2619-9831