Design of Power Efficient Approximate Multiplier Using Enhanced Adder Compressors

Abstract

This study shows a new design for an approximation unsigned multiplier that keeps good computational accuracy while cutting down on size and power use significantly. The suggested design has three main parts: the lower essential portion (LEP), the middle essential portion (MEP), and the accurate region. In the LEP, a preset compensation term takes the role of partial products (PPs). This makes the hardware more efficient without losing accuracy. Two new approximate compressors are used in the approximate region to lower the PPs even more. To reduce errors made by these compressors, a special and effective error-correcting module is built in. The testing on the 8-bit multiplier shows that the suggested designs can improve power by up to 43.71% compared to the exact multiplier. The proposed architecture achieves up to 23.41% more power savings and up to 31.9% better power-delay product than other approximate architectures. Moreover, the proposed designs' practical usefulness is substantiated by assessments in image processing and neural network inference tasks.

Cite this article as: D., P. Upendranath and V. Krishnanaik, “Design of power efficient approximate multiplier using enhanced adder compressors,” Electrica, 2026, 26, 0348, doi: 10.5152/electrica.2026.25348.