Capacitance Multiplier Using Improved Floating Current Sources

In this article, a capacitance multiplier circuit employing improved floating current sources (FCSs) is proposed. The circuit consists of three FCSs and two grounded capacitors, making it suitable for analog integrated circuit (IC) implementations. The use of grounded capacitors simplifies the integration process and enhances circuit stability. The proposed design aims to minimize chip area by replacing large passive capacitors with electronically controllable active structures. The transconductance of the FCSs can be adjusted via bias currents, allowing electronic tuning of the equivalent capacitance. To validate the proposed design, a first-order resistor-capacitor (RC) low-pass filter is implemented and simulated using LTSPICE with TSMC CMOS 0.18 μm process parameters. Simulation results show that the circuit provides a multiplication factor of approximately 10, maintains stable capacitive behavior up to 100 MHz, and exhibits good agreement with the ideal response. In addition, a temperature analysis is performed on the filter circuit to evaluate its thermal robustness, demonstrating minimal variation in gain and cutoff frequency across the tested temperature range. Noise analysis of the implemented low-pass filter indicates low output voltage noise, further confirming the design's suitability for low-noise analog applications. These results confirm the suitability of the proposed circuit for compact, low-voltage, and temperature-stable analog applications.